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Interface Timing

Interface Timing

Fig.10 Interface Timing of CIG Driver
Fig. 10 - Interface Timing of CIG Driver

The CLK input of the CIG driver shows a cycle time of 500ns equating to a 2MHz clock. Improvements have enabled clock rates up to 8MHz to be possible, but the interconnection method and interference may not support this speed. Please check the specification, minimize signal over-shoot, cross-talk and noise to prevent spurious data errors.

In most applications the latch signal is applied when the data clock is idle (H)igh since any positive going cross-talk spike will not cause a false clock.

Static Drive Type

Fig.11 Application Circuit for Static Drive

For static drive, control the CIG VFD from a Serial I/0 as shown in Fig. 11. A standard CPU is sufficient and due to the relatively low software overhead, it is also possible to control the CIG VFD by a standard parallel I/0 port.

Since there is no multiplex drive, the latch and blanking can be connected unless brightness control is required.

 

 

 

Multiplex Drive Type
Fig.12 Application Circuit for Multiplex Drive Type
Fig.12 Application Circuit for Multiplex Drive Type

To achieve a sufficient refresh rate, assign at least one serial I/0 port exclusively for controlling the CIG VFD. Fig. 12 shows an example of the independent grid/anode type, but can be used for the hybrid interlaced grid/anode type as well.

In case the CPU is interrupted for some reason during multiplex driving, the grid scan may stop. This will cause permanent damage to the CIG VFD. To protect the VFD, create a watchdog protection circuit which detects the grid scanning operation and will initiate grid blanking or switch off the display supply voltage "VDD2". Fig. 12 gives an example of a protection circuit using a monostable and OR gate. When the grid scan serial data output of "GSO" is interupted, the monostable is no longer re-triggered and "GBK" sets "High" so that all driver outputs will be OFF.

 

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